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71M6543F/71M6543G Data Sheet
For example, if LCD_MAP[46] = 1, then pin 93 (TMUX2OUT/SEG46) is configured as SEG46, and if
LCD_MAP[46]=0 , then pin 93 is configured as TMUX2OUT.
The SEG pins with alternate ICE interface function (see pins 56-58 in Figure 42 ) are forced to their
alternate ICE interface function (i.e., E_RXTX, E_TCLK and E_RST) if the ICE_E pin (pin 59) is driven
high, and in this case, the bits LCD_MAP[50:48] ( I/O RAM 0x2405[2:0] ) bits are “don’t care” bits. If the
ICE_E pin is driven low, then LCD_MAP[50:48] bits must written with 1 in order to configure these pins as
SEG pins. If the ICE_E pin is low and LCD_MAP[50:48] are written with 0, then these pins are tied to an
internal pullup.
2.5.11 EEPROM Interface
The 71M6543 provides hardware support for either a two-pin or a three-wire (μ-wire) type of EEPROM
interface. The interfaces use the EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E) registers for communication.
2.5.11.1 Two-pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is
multiplexed onto the SEGDIO2 (SDCK) and SEGDIO3 (SDATA) pins and is selected by setting
DIO_EEX[1:0] = 01 ( I/O RAM 0x2456[7:6] ). The MPU communicates with the interface through the SFR
registers EEDATA and EECTRL . If the MPU wishes to write a byte of data to the EEPROM, it places the
data in EEDATA and then writes the Transmit code to EECTRL . This initiates the transmit operation which
is finished when the BUSY bit falls. INT5 is also asserted when BUSY falls. The MPU can then check the
RX_ACK bit to see if the EEPROM acknowledged the transmission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA . The serial transmit and receive clock is 78 kHz during each
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the two-pin
interface is selected are shown in Table 54 .
Table 54: EECTRL Bits for 2-pin Interface
Status
Bit
7
6
5
4
Name
ERROR
BUSY
RX_ACK
TX_ACK
Read/
Write
R
R
R
R
Reset
State
0
0
1
1
Polarity
Positive
Positive
Positive
Positive
Description
1 when an illegal command is received.
1 when serial data bus is busy.
1 indicates that the EEPROM sent an ACK bit.
1 indicates when an ACK bit has been sent to the
EEPROM.
No-op command. Stops the I C clock
CMD[3:0]
0000
Operation
2
(SDCK). If not issued, SDCK keeps
toggling.
3:0
CMD[3:0]
W
0000
Positive
0010
0011
Receive a byte from the EEPROM and
send ACK.
Transmit a byte to the EEPROM.
0101
0110
1001
Others
Issue a STOP sequence.
Receive the last byte from the
EEPROM and do not send ACK.
Issue a START sequence.
No operation, set the ERROR bit.
The EEPROM interface can also be operated by controlling the DIO2 and DIO3 pins directly. The
direction of the DIO line can be changed from input to output and an output value can be written
with a single write operation, thus avoiding collisions (see Table 14 Port Registers (SEGDIO0-15) ).
Therefore, no resistor is required in series SDATA to protect against collisions.
v2
65
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